`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,0
	input data_valid,
	output reg match
	);
    
//detect 0110
localparam IDLE=8'b00000000;
localparam S1=8'b00000001;
localparam S2=8'b00000010;
localparam S3=8'b00000100;
localparam S4=8'b00001000;

reg [7:0]state;
reg [7:0]next_state;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		state<=IDLE;
	end
	else begin
		state<=next_state;
	end
end
always@(*)begin
	case(state)
		IDLE:begin
			//match=1'b0;
			next_state=data_valid?((data==0)?S1:IDLE):state;
		end
		S1:begin
			//match=1'b0;
			next_state=data_valid?((data==1)?S2:S1):state;
		end
		S2:begin
			//match=1'b0;
			next_state=data_valid?((data==1)?S3:S1):state;
		end
		S3:begin
			//match=1'b0;
			next_state=data_valid?((data==0)?S4:IDLE):state;
		end
		S4:begin
			//match=1'b0;
			next_state=data_valid?((data==0)?S1:S2):IDLE;
		end
		default:begin
			//match=1'b0;
			next_state=IDLE;
		end
	endcase
end

always@(*)begin
    if(!rst_n)begin
        match=1'b0;
    end
    else begin
        match=state==S4;
    end
end


endmodule